Non-volatile memory array with memory gate line and source line scrambling
US10192627B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2018 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Apr 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.