Chun Chen
55Patents
4h-index
37Co-inventors
66Inventor score
Filing activity: Dec 17, 1997 → Jun 26, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9853039B1 | Split-gate flash cell formed on recessed substrate | Electricity | 11 | Active |
| US9368606B2 | Memory first process flow and device | Electricity | 8 | Active |
| US8822289B2 | High voltage gate formation | Electricity | 7 | Active |
| US8441063B2 | Memory with extended charge trapping layer | Electricity | 5 | Active |
| US10014380B2 | Memory first process flow and device | Electricity | 4 | Active |
| US9209197B2 | Memory gate landing pad made from dummy features | Electricity | 3 | Active |
| US9881683B1 | Suppression of program disturb with bit line and select gate voltage regulation | Physics | 3 | Active |
| US9917166B2 | Memory first process flow and device | Electricity | 3 | Active |
| US10872898B2 | Embedded non-volatile memory device and fabrication method of the same | Electricity | 3 | Active |
| US10685724B2 | Suppression of program disturb with bit line and select gate voltage regulation | Physics | 2 | Active |
| US8836006B2 | Integrated circuits with non-volatile memory and methods for manufacture | Electricity | 2 | Active |
| US6058650A | Planting apparatus and method for green plants on reinforced concrete structures | Human Necessities | 2 | Expired |
| US9997253B1 | Non-volatile memory array with memory gate line and source line scrambling | Electricity | 2 | Active |
| US9589805B2 | Split-gate semiconductor device with L-shaped gate | Electricity | 2 | Active |
| US8076199B2 | Method and device employing polysilicon scaling | Electricity | 1 | Active |
| US8686492B2 | Non-volatile FINFET memory device and manufacturing method thereof | Electricity | 1 | Active |
| US8785275B2 | Non-volatile FINFET memory device and manufacturing method thereof | Electricity | 1 | Active |
| US8598646B2 | Non-volatile FINFET memory array and manufacturing method thereof | Electricity | 1 | Active |
| US10141393B1 | Three dimensional capacitor | Electricity | 1 | Active |
| US10242996B2 | Method of forming high-voltage transistor with thin gate poly | Electricity | 1 | Active |
| USD444467S | Computer mainframe | General | 1 | Expired |
| US9052871B2 | Recess for memory card | Physics | 1 | Active |
| US10229745B2 | Suppression of program disturb with bit line and select gate voltage regulation | Physics | 1 | Active |
| US12029041B2 | Method of forming high-voltage transistor with thin gate poly | Electricity | 1 | Active |
| US8202779B2 | Methods for forming a memory cell having a top oxide spacer | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.