Layered semiconductor substrate with reduced bow having a group III nitride layer and method for manufacturing it

US10192739B2 · kind B2 · utility

Assignee

• Siltronic AG · DE

Inventors

• Peter Storck · Mehring, DE
• Guenter Sachs · Herzogenaurach, DE
• Ute Rothammer · Mehring, DE
• Sarad Bahadur Thapa · Burghausen, DE
• Helmut Schwenk · Burghausen, DE
• Peter Dreier · Burghausen, DE
• Frank Muemmler · Emmerting, DE
• Rudolf Mayrhuber

Key dates

• Filing date: May 23, 2012
• Grant date: Jan 29, 2019
• Expiry date: Dec 31, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/0262
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A layered semiconductor substrate has a monocrystalline first layer based on silicon, having a first thickness and a first lattice constant a1 determined by a first dopant element and a first dopant concentration, and in direct contact therewith, a monocrystalline second layer based on silicon, having a second thickness and a second lattice constant a2, determined by a second dopant element and a second dopant concentration, and a monocrystalline third layer comprising a group III nitride, the second layer located between the first layer and the third layer, wherein a2>a1, wherein the crystal lattice of the first layer and the second layer are lattice-matched, and wherein the bow of the layered semiconductor substrate is in the range from −50 μm to 50 μm.