Controlling of etch depth in deep via etching processes and resultant structures
US10192748B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Oct 19, 2016 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Oct 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/26
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to semiconductor structures and, more particularly, to a method to control depth of etch in deep via etching and related structures. The method includes: forming an interface within the substrate between an etch control dopant and material of the substrate; etching a via within substrate; and terminating the etching of the via at the interface upon detection of the interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.