Methods of fabricating dual threshold voltage devices with stacked gates
US10192788B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2018 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Jan 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.