Amitay Levi
63Patents
7h-index
32Co-inventors
72Inventor score
Filing activity: Jul 26, 2001 → Jul 9, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7868375B2 | Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing | Electricity | 138 | Active |
| US7315056B2 | Semiconductor memory array of floating gate memory cells with program/erase and select gates | Physics | 77 | Expired |
| US7927994B1 | Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing | Electricity | 46 | Active |
| US7149110B2 | Seek window verify program system and method for a multilevel non-volatile memory integrated circuit system | Physics | 32 | Expired |
| US6855980B2 | Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling | Electricity | 21 | Expired |
| US6727545B2 | Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling | Electricity | 20 | Expired |
| US8148768B2 | Non-volatile memory cell with self aligned floating and erase gates, and method of making same | Electricity | 14 | Active |
| US6566706B1 | Semiconductor array of floating gate memory cells and strap regions | Electricity | 7 | Expired |
| US7227217B2 | Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing | Electricity | 7 | Expired |
| US10192789B1 | Methods of fabricating dual threshold voltage devices | Electricity | 7 | Active |
| US7829404B2 | Method of making a semiconductor memory array of floating gate memory cells with program/erase and select gates | Physics | 6 | Active |
| US8962493B2 | Magnetic random access memory cells having improved size and shape characteristics | Electricity | 6 | Active |
| US10355045B1 | Three dimensional perpendicular magnetic junction with thin-film transistor | Electricity | 5 | Active |
| US7816723B2 | Semiconductor memory array of floating gate memory cells with program/erase and select gates | Physics | 4 | Active |
| US10236075B1 | Predicting tunnel barrier endurance using redundant memory structures | Physics | 4 | Active |
| US10186551B1 | Buried tap for a vertical transistor used with a perpendicular magnetic tunnel junction (PMTJ) | Electricity | 4 | Active |
| US10468293B2 | Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channels | Electricity | 4 | Active |
| US10333063B1 | Fabrication of a perpendicular magnetic tunnel junction (PMTJ) using block copolymers | Electricity | 4 | Active |
| US10192788B1 | Methods of fabricating dual threshold voltage devices with stacked gates | Electricity | 4 | Active |
| US8138524B2 | Self-aligned method of forming a semiconductor memory array of floating memory cells with source side erase, and a memory array made thereby | Electricity | 4 | Active |
| US10937479B1 | Integration of epitaxially grown channel selector with MRAM device | Physics | 4 | Active |
| US7851846B2 | Non-volatile memory cell with buried select gate, and method of making same | Electricity | 4 | Active |
| US7084453B2 | Method of forming different oxide thickness for high voltage transistor and memory cell tunnel dielectric | Emerging Cross-Sectional Technologies | 4 | Expired |
| US10658425B2 | Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channels | Electricity | 4 | Active |
| US8384147B2 | High endurance non-volatile memory cell and array | Electricity | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.