Conductive layout structure including high resistive layer
US10192826B2 · kind B2 · utility
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18References
8Claims
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Key dates
| Filing date | Dec 26, 2017 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Dec 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/257
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.