Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems
US10198362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2017 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Mar 4, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems is disclosed. In this regard, a memory system including a compression circuit is provided. The compression circuit includes a compress circuit that is configured to cache free memory lists using free memory list caches comprising a plurality of buffers. When a number of pointers cached within the free memory list cache falls below a low threshold value, an empty buffer of the plurality of buffers is refilled from a system memory. In some aspects, when a number of pointers of the free memory list cache exceeds a high threshold value, a full buffer of the free memory list cache is emptied to the system memory. In this manner, memory access operations for emptying and refilling the free memory list cache may be minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.