Technique for defining active regions of semiconductor devices with reduced lithography effort

US10199259B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Elliot John Smith · Dresden, DE
• Michael Zier · Dresden, DE

Key dates

• Filing date: Aug 7, 2017
• Grant date: Feb 5, 2019
• Expiry date: Aug 7, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/308
• WIPO field: Optics
• WIPO sector: Instruments

Abstract

In semiconductor devices requiring the formation of fully depleted SOI transistor elements in combination with non-FET elements, such as substrate diodes and the like, the patterning of the active regions may be accomplished on the basis of deep isolation trenches, which may be formed first on the basis of immersion-based lithography, followed by formation of shallow isolation trenches also formed on the basis of immersion lithography. Thereafter, respective openings connecting to the substrate materials may be formed, possibly in combination with isolation trenches of reduced depth compared to the deep isolation trenches, on the basis of non-immersion lithography techniques. In this manner, device scaling for semiconductor devices requiring critical dimensions of 26 nm and less in a planar transistor architecture may be accomplished.