Semiconductor device and fabrication method thereof
US10199374B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2017 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Nov 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/474
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.