Integrated magnetic random access memory with logic device
US10199572B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2016 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | May 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
Abstract
Device and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first dielectric layer is provided over the first and second regions of the substrate. The first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions. A first interlevel dielectric (ILD) layer is provided over the first dielectric layer. The first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region. A magnetic random access memory (MRAM) cell is formed in the second region. The MRAM cell includes a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.