Semiconductor storage device and memory system
US10204680B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2017 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Sep 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to an embodiment, a control circuitry performing: a first operation of reading data out of a memory cell with a first voltage applied to a word line while changing the first voltage by a first shift amount within a first range, and a second operation of reading data out of the memory cell with a second voltage applied to the word line while changing the second voltage by a second shift amount within a second range, wherein the second shift amount is smaller than the first shift amount, and wherein the control circuitry performs the second operation to apply the second voltage to the word line subsequently to application of the first voltage to the word line in the first operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.