Method to reduce program disturbs in non-volatile memory cells

US10204691B2 · kind B2 · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• Ryan T. Hirose · Colorado Springs, US
• Igor G. Kouznetsov · San Jose, US
• Venkatraman Prabhakar · Pleasanton, US
• Kaveh Shakeri · Campbell, US
• Bogdan I. Georgescu · Colorado Springs, US

Key dates

• Filing date: Nov 8, 2017
• Grant date: Feb 12, 2019
• Expiry date: Nov 8, 2037

Classification

• Technology area (CPC —): General

Abstract

A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array.