Methods, apparatus, and system for reducing step height difference in semiconductor devices

US10204797B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Jinsheng Gao · Clifton Park, US
• Daniel Jaeger · Saratoga Springs, US
• Michael V. Aquilino · Wappingers Falls, US
• Patrick Carpenter · Saratoga Springs, US
• Junsic Hong · Malta, US
• Jessica Dechene · Watervliet, US
• Haigou Huang · Rexford, US

Key dates

• Filing date: Feb 6, 2018
• Grant date: Feb 12, 2019
• Expiry date: Feb 6, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/67063
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The disclosed methods may include depositing an amorphous carbon layer, a SiCN layer, and a TEOS layer; planarizing the semiconductor structure; performing a non-selective etch to remove the SiCN layer, the TEOS layer, and a portion of the amorphous carbon layer; and performing a selective etch of the amorphous carbon layer. The methods may reduce step height differences between first and second regions of the semiconductor structure.