Inventor · Saratoga Springs, NY, US

Daniel Jaeger

35Patents
6h-index
72Co-inventors
68Inventor score

Filing activity: Mar 30, 2009 → Nov 8, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US8053301B2 CMOS SiGe channel pFET and Si channel nFET devices with minimal STI recess Electricity 24 Active
US10269654B1 Methods, apparatus and system for replacement contact for a finFET device Electricity 9 Active
US10325819B1 Methods, apparatus and system for providing a pre-RMG replacement metal contact for a finFET device Electricity 9 Active
US8129234B2 Method of forming bipolar transistor integrated with metal gate CMOS devices Electricity 9 Active
US9035430B2 Semiconductor fin on local oxide Electricity 6 Active
US9761452B1 Devices and methods of forming SADP on SRAM and SAQP on logic Electricity 6 Active
US9041076B2 Partial sacrificial dummy gate with CMOS device with high-k metal gate Electricity 3 Active
US10644156B2 Methods, apparatus, and system for reducing gate cut gouging and/or gate height loss in semiconductor devices Electricity 3 Active
US9299795B2 Partial sacrificial dummy gate with CMOS device with high-k metal gate Electricity 3 Active
US10204797B1 Methods, apparatus, and system for reducing step height difference in semiconductor devices Electricity 2 Active
US10340142B1 Methods, apparatus and system for self-aligned metal hard masks Electricity 2 Active
US10373875B1 Contacts formed with self-aligned cuts Electricity 2 Active
US9589829B1 FinFET device including silicon oxycarbon isolation structure Electricity 2 Active
US10833160B1 Field-effect transistors with self-aligned and non-self-aligned contact openings Electricity 2 Active
US10418455B2 Methods, apparatus and system for stringer defect reduction in a trench cut region of a finFET device Electricity 1 Active
US8629028B2 Metal oxide semiconductor field effect transistor (MOSFET) gate termination Electricity 1 Active
US10991796B2 Source/drain contact depth control Electricity 1 Active
US8415212B2 Method of enhancing photoresist adhesion to rare earth oxides Electricity 1 Active
US9780002B1 Threshold voltage and well implantation method for semiconductor devices Electricity 1 Active
US10971625B2 Epitaxial structures of a semiconductor device having a wide gate pitch Electricity 0 Active
US10522639B2 Methods, apparatus and system for stringer defect reduction in a trench cut region of a finFET device Electricity 0 Active
US10460986B2 Cap structure Electricity 0 Active
US10930549B2 Cap structure Electricity 0 Active
US10714376B2 Method of forming semiconductor material in trenches having different widths, and related structures Electricity 0 Active
US10062612B2 Method and system for constructing FINFET devices having a super steep retrograde well Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.