Enabling low resistance gates and contacts integrated with bilayer dielectrics

US10204828B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ruqiang Bao · Niskayuna, US
• Benjamin D. Briggs · Cohoes, US
• Lawrence A. Clevenger · Saratoga Springs, US
• Koichi Motoyama · Clifton Park, US
• Cornelius Brown Peethala · Slingerlands, US
• Michael Rizzolo · Delmar, US
• Gen Tsutsui · Yokohama, JP

Key dates

• Filing date: Feb 9, 2018
• Grant date: Feb 12, 2019
• Expiry date: Feb 9, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0144
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for forming a semiconductor structure using first and second conductive materials, and having first and second trenches with first and second critical dimensions. The second conductive material exhibits a lower resistivity than the first conductive material at a film thickness corresponding to the second critical dimension and the second conductive material exhibits a higher resistivity than the first conductive material at a film thickness corresponding to the first critical dimension. An initial semiconductor structure has the first trench having the first critical dimension and the second trench having the second critical dimension. The second critical dimension is larger than the first critical dimension. A first conductive structure made from one of the first and second conductive materials is formed in the first trench. A second conductive structure made from another of the first and second conductive materials is formed in the second trench.