Temporary connection traces for wafer sort testing
US10204841B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2016 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Dec 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/94
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating integrated circuit (IC) dies and wafers having such dies, are disclosed herein that leverage temporary connection traces during wafer level testing of the functionality of the IC die. In one example, a wafer includes a plurality of IC dies. At least a first IC die of the plurality of IC dies includes a plurality of micro-bumps and a first temporary connection trace formed on an exterior surface of the die body. The plurality of micro-bumps includes at least a first micro-bump and a second micro-bump. The first temporary connection trace electrically couples the first micro-bump and the second micro-bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.