Inventor · Mountain View, CA, US

Raghunandan Chaware

22Patents
7h-index
23Co-inventors
65Inventor score

Filing activity: Jul 22, 2005 → Jul 15, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US8704384B2 Stacked die assembly Electricity 63 Active
US8415783B1 Apparatus and methodology for testing stacked die Electricity 24 Active
US9865567B1 Heterogeneous integration of integrated circuit device and companion device Electricity 24 Active
US7863092B1 Low cost bumping and bonding method for stacked die Electricity 16 Active
US9418909B1 Stacked silicon package assembly having enhanced lid adhesion Electricity 14 Active
US7906857B1 Molded integrated circuit package and method of forming a molded integrated circuit package Electricity 14 Active
US10602612B1 Vertical module and perpendicular pin array interconnect for stacked circuit board structure Emerging Cross-Sectional Technologies 10 Active
US7338842B2 Process for exposing solder bumps on an underfill coated semiconductor Electricity 6 Active
US8841752B1 Semiconductor structure and method for interconnection of integrated circuits Electricity 5 Active
US8519528B1 Semiconductor structure and method for interconnection of integrated circuits Electricity 5 Active
US8766086B2 System and method for laminating photovoltaic structures Emerging Cross-Sectional Technologies 5 Active
US9385106B1 Method for providing charge protection to one or more dies during formation of a stacked silicon device Electricity 5 Active
US10032682B1 Multi-die wafer-level test and assembly without comprehensive individual die singulation Electricity 2 Active
US9761533B2 Interposer-less stack die interconnect Electricity 2 Active
US8900987B1 Method for removing bumps from incomplete and defective interposer dies for stacked silicon interconnect technology (SSIT) devices Electricity 1 Active
US9989572B1 Method and apparatus for testing interposer dies prior to assembly Physics 1 Active
US10840192B1 Stacked silicon package assembly having enhanced stiffener Electricity 1 Active
US9341668B1 Integrated circuit package testing Physics 1 Active
US10638608B2 Interconnect frames for SIP modules Electricity 1 Active
US11075117B2 Die singulation and stacked device structures Electricity 0 Active
US10204841B1 Temporary connection traces for wafer sort testing Electricity 0 Active
US8361259B2 System and method for determining placement of photovoltaic strips using displacement sensors Emerging Cross-Sectional Technologies 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.