Reduced gate charge field-effect transistor

US10205015B2 · kind B2 · utility

Assignee

• Infineon Technologies Austria AG · AT

Inventors

• David Laforet · Villach, AT
• Li Juin Yip · Villach, AT
• Cedric Ouvrard · Villach, AT

Key dates

• Filing date: Aug 17, 2017
• Grant date: Feb 12, 2019
• Expiry date: Aug 17, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/516

Abstract

In one implementation, a reduced gate charge field-effect transistor (FET) includes a drift region situated over a drain, a body situated over the drift region, and source diffusions formed in the body. The source diffusions are adjacent a gate trench extending through the body into the drift region and having a dielectric liner and a gate electrode situated therein. The dielectric liner includes an upper segment and a lower segment, the upper segment extending to at least a depth of the source diffusions and being significantly thicker than the lower segment.