Planar double gate semiconductor device

US10205018B1 · kind B1 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Xia Li · San Diego, US
• Bin Yang · San Diego, US
• Gengming Tao · San Diego, US

Key dates

• Filing date: Aug 14, 2017
• Grant date: Feb 12, 2019
• Expiry date: Aug 14, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/882

Abstract

Certain aspects of the present disclosure generally relate to a semiconductor device. The semiconductor device generally includes a substrate, a channel disposed above the substrate, and a first dielectric layer disposed adjacent to a first side of the channel. The semiconductor device may also include a first non-insulative region disposed between the first dielectric layer and the substrate, and a second dielectric layer disposed adjacent to a second side of the channel, wherein the first dielectric layer and the second dielectric layer comprise high-k layers. In certain aspects, a second non-insulative region may be disposed above the second dielectric layer, and a third non-insulative region may be disposed adjacent to a third side of the channel.