Low latency soft decoder architecture for generalized product codes
US10205469B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2017 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Mar 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2957
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques for reducing the latency for decoding product codewords with minimal hardware architecture changes are described. In an example, a system accesses and decodes a generalized product code (GPC) codeword by using at least one of a plurality of Chase decoding procedures available on the system. A first Chase decoding procedure is configured according to first values for a set of decoding parameters. A second Chase decoding procedure is configured according to second values for the set of decoding parameters. The second values are different from the first values. The first Chase decoding procedure has a smaller latency and a higher bit error rate (BER) relative to the second Chase decoding procedure based on the first values and the second values for the set of decoding parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.