Reducing injection type of read disturb in a cold read of a memory device
US10210941B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2018 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Jan 24, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and associated techniques for optimizing the channel boosting level in an unselected NAND string during a read operation for a selected NAND string. A tracking circuit tracks an indicator of a floating voltage of unselected word lines of a block. For example, this can include tracking a time since a last sensing operation, and determining whether a power on event has occurred without a subsequent sensing operation. In response to a read command, the indicator is used to set parameters in the read operation which can reduce disturbs. This can include setting a duration and/or a magnitude of a select gate voltage pulse during the increase of the voltage of the unselected word lines. The duration and/or a magnitude of the control gate voltage pulse can also be set based on a temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.