Inventor · San Jose, CA, US

Hong-Yan Chen

44Patents
12h-index
19Co-inventors
74Inventor score

Filing activity: Mar 3, 2014 → Jul 20, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US9286987B1 Controlling pass voltages to minimize program disturb in charge-trapping memory Physics 42 Active
US9336892B1 Reducing hot electron injection type of read disturb in 3D non-volatile memory Physics 39 Active
US9286994B1 Method of reducing hot electron injection type of read disturb in dummy memory cells Physics 38 Active
US9412463B1 Reducing hot electron injection type of read disturb in 3D non-volatile memory for edge word lines Physics 37 Active
US9361993B1 Method of reducing hot electron injection type of read disturb in memory Physics 35 Active
US9640273B1 Mitigating hot electron program disturb Physics 29 Active
US9761320B1 Reducing hot electron injection type of read disturb during read recovery phase in 3D memory Physics 25 Active
US9747992B1 Non-volatile memory with customized control of injection type of disturb during read operations Physics 23 Active
US10283202B1 Reducing disturbs with delayed ramp up of selected word line voltage after pre-charge during programming Physics 14 Active
US9406391B1 Method of reducing hot electron injection type of read disturb in dummy memory cells Physics 14 Active
US9349478B2 Read with look-back combined with programming with asymmetric boosting in memory Physics 14 Active
US9165659B1 Efficient reprogramming method for tightening a threshold voltage distribution in a memory device Physics 13 Active
US10636500B1 Reducing read disturb in two-tier memory device by modifying ramp up rate of word line voltages during channel discharge Electricity 12 Active
US10026487B2 Non-volatile memory with customized control of injection type of disturb during program verify for improved program performance Physics 12 Active
US10770157B1 Method of reducing injection type of program disturb during program pre-charge in memory device Physics 11 Active
US10153051B1 Program-verify of select gate transistor with doped channel in NAND string Physics 11 Active
US10629272B1 Two-stage ramp up of word line voltages in memory device to suppress read disturb Physics 10 Active
US9905305B2 Reducing hot electron injection type of read disturb in 3D non-volatile memory for edge word lines Physics 10 Active
US10438671B1 Reducing program disturb by modifying word line voltages at interface in two-tier stack during programming Physics 10 Active
US9324439B1 Weak erase after programming to improve data retention in charge-trapping memory Physics 9 Active
US10522232B2 Memory device with vpass step to reduce hot carrier injection type of program disturb Electricity 8 Active
US10269435B1 Reducing program disturb by modifying word line voltages at interface in two-tier stack after program-verify Physics 8 Active
US10790003B1 Maintaining channel pre-charge in program operation Physics 7 Active
US10210941B1 Reducing injection type of read disturb in a cold read of a memory device Physics 7 Active
US10665306B1 Memory device with discharge voltage pulse to reduce injection type of program disturb Physics 7 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.