Metal-insulator-metal capacitors with dielectric inner spacers
US10211147B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2017 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Dec 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53295
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. A layer stack is deposited that includes a first conductor layer, a second conductor layer, and a third conductor layer. The layer stack is patterned to define a first electrode of the MIM capacitor from the first conductor layer, a second electrode of the MIM capacitor from the second conductor layer, and a third electrode of the MIM capacitor from the third conductor layer. A via opening is formed that extends vertically through the layer stack. The first electrode is recessed relative to the second electrode to define a cavity that is laterally offset from the via opening. A dielectric inner spacer is formed in the cavity. A conductive via is formed in the first via opening after the dielectric inner spacer is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.