Semiconductor package manufacturing method
US10211164B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2017 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Dec 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A plurality of semiconductor packages are manufactured by a method that includes the steps of bonding a plurality of semiconductor chips on the front side of a wiring substrate, next supplying a sealing compound to the front side of the wiring substrate to form a resin layer from the sealing component on the front side of the wiring substrate, thereby forming a sealed substrate including the wiring substrate and the resin layer covering the semiconductor chips, next cutting the sealed substrate from the resin layer side by using a V blade to thereby form a V groove along each division line, next dividing the wiring substrate along each V groove to obtain a plurality of individual bare packages, and finally forming an electromagnetic shield layer on the upper surface and an inclined side surface of each bare package, thereby obtaining the plural semiconductor packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.