Patent · US Active

Package-on-package stacked microelectronic structures

US10211182B2 · kind B2 · utility

42Cited by

6References

25Claims

0Family size

Assignee

Intel IP Corporation · US

Inventors

Thorsten Meyer · Regensburg, DE
Gerald Ofner · Regensburg, DE

Key dates

Filing date	Jul 7, 2014
Grant date	Feb 19, 2019
Priority date	—
Expiry date	Jul 7, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH05K2201/10515
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A package-on-package stacked microelectronic structure comprising a pair of microelectronic packages attached to one another in a flipped configuration. In one embodiment, the package-on-package stacked microelectronic structure may comprise a first and a second microelectronic package, each comprising a substrate having at least one package connection bond pad formed on a first surface of each microelectronic package substrate, and each having at least one microelectronic device electrically connected to the each microelectronic package substrate first surface, wherein the first and the second microelectronic package are connected to one another with at least one package-to-package interconnection structure extending between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.