Methods of manufacturing inner spacers in a gate-all-around (GAA) FET through multi-layer spacer replacement
US10211307B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2017 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Jul 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6757
Abstract
In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.