Ferroelectric memory device and fabrication method thereof
US10211312B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2016 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Aug 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02568
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosed technology generally relates to semiconductor devices, and more particularly to a non-volatile ferroelectric memory device and to methods of fabricating the same. In one aspect, a non-volatile memory device includes a high dielectric constant layer (high-k) layer or a metal layer on a semiconductor substrate. The non-volatile memory device additionally includes a two-dimensional (2D) semiconductor channel layer interposed between the high-k layer or metal layer and a ferroelectric layer. The non-volatile memory device additionally includes a metal gate layer on the ferroelectric layer, and further includes a source region and a drain region each electrically coupled to the 2D semiconductor channel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.