Substantially defect-free polysilicon gate arrays
US10217633B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Mar 13, 2017 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Mar 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A single critical mask process flow and associated structure eliminate the formation of narrow polysilicon defects at the ends of polysilicon gate arrays, and obviate the need to implement complicated ground rules and post-design fill methods to avoid generation of the defects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.