Inventor · Watervliet, NY, US

Daniel James Dechene

23Patents
2h-index
47Co-inventors
53Inventor score

Filing activity: Jan 18, 2013 → Oct 15, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US8656322B1 Fin design level mask decomposition for directed self assembly Electricity 21 Active
US9252022B1 Patterning assist feature to mitigate reactive ion etch microloading effect Electricity 14 Active
US10833160B1 Field-effect transistors with self-aligned and non-self-aligned contact openings Electricity 2 Active
US11515427B2 Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance Electricity 2 Active
US10998193B1 Spacer-assisted lithographic double patterning Electricity 2 Active
US10170309B2 Dummy pattern addition to improve CD uniformity Electricity 1 Active
US9780002B1 Threshold voltage and well implantation method for semiconductor devices Electricity 1 Active
US11977614B2 Circuit design watermarking Electricity 0 Active
US11888048B2 Gate oxide for nanosheet transistor devices Electricity 0 Active
US10691862B2 Layouts for connecting contacts with metal tabs or vias Electricity 0 Active
US11024551B1 Metal replacement vertical interconnections for buried capacitance Electricity 0 Active
US11158536B2 Patterning line cuts before line patterning using sacrificial fill material Electricity 0 Active
US12068415B2 Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance Electricity 0 Active
US11830778B2 Back-side wafer modification Electricity 0 Active
US12400871B2 Metal lines with low via-to-via spacing Electricity 0 Active
US11527434B2 Line cut patterning using sacrificial material Electricity 0 Active
US12363965B2 Stacked transistor layout for improved cell height scaling Electricity 0 Active
US11257681B2 Using a same mask for direct print and self-aligned double patterning of nanosheets Electricity 0 Active
US11211474B2 Gate oxide for nanosheet transistor devices Electricity 0 Active
US10332745B2 Dummy assist features for pattern support Electricity 0 Active
US12080559B2 Using a same mask for direct print and self-aligned double patterning of nanosheets Electricity 0 Active
US10867912B2 Dummy fill scheme for use with passive devices Electricity 0 Active
US10217633B2 Substantially defect-free polysilicon gate arrays Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.