Method and structure for minimizing fin reveal variation in FinFET transistor
US10217658B2 · kind B2 · utility
2Cited by
6References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2018 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Jan 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a plurality of fins spaced apart from each other on a substrate; a liner layer on the substrate between each fin of the plurality of fins and on at least a portion of a sidewall of each fin; and a plurality of isolation regions adjacent and between the plurality of fins. The plurality of isolation regions are on a top surface of the liner layer on the substrate and includes a dielectric layer; and a doped region on the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.