Technique for patterning active regions of transistor elements in a late manufacturing stage
US10217660B2 · kind B2 · utility
1Cited by
1References
20Claims
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Key dates
| Filing date | Jul 18, 2017 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Jul 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0135
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
When patterning active regions for sophisticated semiconductor devices, the cutting through active semiconductor regions previously patterned along a first lateral direction so as to obtain elongated semiconductor lines may be performed in a late manufacturing stage. That is, the cutting may be performed after patterning at least a portion of the gate electrode structures, thereby achieving a self-aligned patterning regime and also contributing to a reduction of strain loss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.