Integrated circuit device with source/drain barrier
US10217815B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2017 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Oct 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3065
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.