Method for making a semiconductor device with self-aligned inner spacers
US10217842B2 · kind B2 · utility
3Cited by
1References
13Claims
0Family size
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Key dates
| Filing date | Dec 11, 2017 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Dec 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/015
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a semiconductor device, including:
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.