Method of forming pairs of three-gate non-volatile flash memory cells using two polysilicon deposition steps

US10217850B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Feng Zhou · Ann Arbor, US
• Xian Liu · Sunnyvale, US
• Chien-Sheng Su · Saratoga, US
• Nhan Do · Saratoga, US
• Chunming Wang · Nanhu, CN

Key dates

• Filing date: Mar 30, 2017
• Grant date: Feb 26, 2019
• Expiry date: Mar 30, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/015

Abstract

A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).