ECC decoder with multiple decoding modes
US10218384B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2016 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Dec 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6577
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes a message memory configured to store decoding messages, multiple data processing units (DPUs), a control circuit, and a reording circuit. The control circuit is configured to enable a first number of the DPUs to decode the representation of the codeword in response to a decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode. The reordering circuit is configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.