Generation of network-on-chip layout based on user specified topological constraints
US10218581B2 · kind B2 · utility
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2Claims
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Key dates
| Filing date | Jun 21, 2018 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Jun 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In an aspect, the present disclosure provides a method that comprises automatic generation of a NoC from specified topological information based on projecting NoC elements of the NoC onto a grid layout. In an aspect, the specified topological information, including specification of putting constraints on positions/locations of NoC elements and links thereof, can be input by a user in real space, and can then be projected on the grid layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.