Memory device with dynamic storage mode control
US10223259B1 · kind B1 · utility
2Cited by
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21Claims
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Key dates
| Filing date | Aug 31, 2017 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Aug 31, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes: a memory array including a plurality of memory cells, the plurality of memory cells including a plurality of cache memory cells; and a controller coupled to the memory array, the controller configured to: track usage of a first subset of the plurality of cache memory cells operating in a single-level cell (SLC) mode, wherein the tracking includes monitoring for an idle time event; and designate a storage mode for a second subset of the plurality of cache memory cells based on the tracked usage of the first subset, wherein the storage mode determines a storage density to be used for data writes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.