Inventor · Boise, ID, US

Peter Feeley

203Patents
12h-index
74Co-inventors
89Inventor score

Filing activity: Jun 13, 1994 → Mar 25, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US8412880B2 Memory system controller to manage wear leveling across a plurality of storage nodes Physics 322 Active
US5532693A Adaptive data compression system with systolic string matching logic Electricity 194 Expired
US10347344B2 Read voltage calibration based on host IO operations Physics 52 Active
US8103936B2 System and method for data read of a synchronous serial interface NAND Physics 24 Active
US7770079B2 Error scanning in flash memory Physics 18 Active
US9921898B1 Identifying asynchronous power loss Physics 18 Active
US8451664B2 Determining and using soft data in memory devices and systems Physics 18 Active
US10359933B2 Memory devices and electronic systems having a hybrid cache including static and dynamic caches with single and multiple bits per cell, and related methods Physics 16 Active
US5734926A Direct memory access controller in an integrated circuit Physics 14 Expired
US9104555B2 Memory system controller Physics 13 Active
US8358542B2 Methods, devices, and systems for adjusting sensing voltages in devices Physics 13 Active
US8077515B2 Methods, devices, and systems for dealing with threshold voltage change in memory devices Physics 13 Active
US8918600B2 Methods for controlling host memory access with memory devices and systems Physics 11 Active
US8356216B2 Error scanning in flash memory Physics 11 Active
US8751860B2 Object oriented memory in solid state devices Physics 11 Active
US9235546B2 System and method for data read of a synchronous serial interface NAND Physics 11 Active
US9208833B2 Sequential memory operation without deactivating access line signals Physics 10 Active
US9318220B2 Memory cell coupling compensation Physics 10 Active
US9269450B2 Methods, devices, and systems for adjusting sensing voltages in devices Physics 9 Active
US10318378B2 Redundant array of independent NAND for a three-dimensional memory array Emerging Cross-Sectional Technologies 8 Active
US10365854B1 Tracking data temperatures of logical block addresses Physics 8 Active
US8250417B2 Method for detecting flash program failures Emerging Cross-Sectional Technologies 8 Active
US9093152B2 Multiple data line memory and methods Electricity 6 Active
US8352833B2 System and method for data read of a synchronous serial interface NAND Physics 6 Active
US9552257B2 Memory cell coupling compensation Physics 6 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.