Memory with a global reference circuit
US10224088B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2018 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Feb 12, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a global reference circuit for generating a signal that controls the resistance of a plurality of reference devices used to read data in memory cells by sense amplifiers of the memory. The signal is generated by an output of an operational amplifier of the global reference circuit. The operational amplifier includes a first input whose voltage is set by flowing current through a reference circuit and a second input whose voltage is set by flowing current through a master reference device. The signal controls the resistance of the master reference device such that the voltages of the inputs of the operational amplifier match.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.