Semiconductor device using a parallel bit operation and method of operating the same
US10224114B2 · kind B2 · utility
3Cited by
7References
17Claims
0Family size
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Key dates
| Filing date | May 20, 2017 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | May 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include a memory cell array including a plurality of memory cells, and an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits and also perform an internal operation including a comparison operation with respect to external data in a normal mode other than the test mode using the parallel bit operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.