Wafer level fan out package and method of fabricating wafer level fan out package
US10224217B1 · kind B1 · utility
6Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2015 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Dec 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.