Multi-layer filled gate cut to prevent power rail shorting to gate structure
US10224246B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2017 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Jun 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5286
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a power rail to semiconductor devices that includes forming a gate structure extending from a first active region to a second active region of a substrate, and removing a portion of the gate structure forming a gate cut trench separating the first active region from the second active region. A fill material of an alternating sequence of at least two different composition conformally deposited dielectric layers is formed within the gate cut trench. A power rail is formed in the gate cut trench. An aspect ratio of the vertically orientated portions of the alternating sequence of the at least two different composition conformally deposited dielectric layer obstructs lateral etching of the gate cut trench during etching to form a power rail opening for housing the power rail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.