Vertical field-effect transistor with uniform bottom spacer
US10229985B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2017 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Dec 4, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor structure includes patterning two or more fins over a top surface of a bottom source/drain layer, the bottom source/drain layer disposed over a substrate. The method also includes forming bottom spacers disposed over the top surface of the bottom source/drain layer between the two or more fins, the bottom spacers having a uniform height on sidewalls of the two or more fins. The bottom spacers comprise dielectric regions disposed adjacent the sidewalls of the two or more fins and at least partially filling divots in the bottom source/drain regions, and liner regions disposed adjacent the dielectric regions. The two or more fins comprise channels for a vertical field-effect transistor (VFET) device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.