Vertical transport field-effect transistor including dual layer top spacer
US10229986B1 · kind B1 · utility
22Cited by
10References
8Claims
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Key dates
| Filing date | Dec 4, 2017 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Dec 4, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a multi-layer top spacer that includes an oxygen barrier layer beneath a top dielectric layer. Techniques for fabricating the transistor include depositing the oxygen barrier layer over the gate stack prior to depositing the top dielectric layer. The oxygen barrier layer blocks oxygen diffusion during deposition of the top dielectric layer, thereby avoiding damage to underlying interfacial and gate dielectric layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.