Fault tolerant memory systems and components with interconnected and redundant data interfaces
US10235242B2 · kind B2 · utility
7Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2016 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | Mar 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.