Debugging system and method
US10235272B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2017 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | Jun 30, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An approach for debugging a circuit implementation of a software specification includes translating a high-level language debugging command into a hardware debugging command that specifies the value(s) of a condition in the circuit implementation, and a storage element(s) at which the value(s) of the condition is stored. The hardware debugging command is transmitted to a debug controller circuit that generates a single clock pulse to the circuit implementation. The debug controller circuit reads a value(s) from the storage element(s) specified by the hardware debugging command and determines whether or not the value(s) satisfies the condition. The debug controller circuit generates another single clock pulse in response to the value(s) read from the storage element(s) not satisfying the condition. Generation of pulses of the clock signal is suspended and data indicative of a breakpoint is output in response to the value(s) read from the storage element(s) satisfying the condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.