Method for PECVD overlay improvement
US10236225B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2018 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | Apr 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure generally relates to a method for performing semiconductor device fabrication, and more particularly, to improvements in lithographic overlay techniques. The method for improved overlay includes depositing a material on a substrate, heating a substrate in a chamber using thermal energy, measuring a local stress pattern of each substrate, wherein measuring the local stress pattern measures an amount of change in a depth of the deposited material on the substrate, plotting a plurality of points on a k map to determine a local stress pattern of the substrate, adjusting the thermal energy applied to the points on the k map, determining a sensitivity value for each of the points on the k map, and applying a correction factor to the applied thermal energy to adjust the local stress pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.