Patent · US Active

Strain retention semiconductor member for channel SiGe layer of pFET

US10236343B2 · kind B2 · utility

0Cited by

1References

12Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Dina H. Triyoso · Mechanicville, US
Timothy J. McArdle · Ballston Lake, US
Judson R. Holt · Wappingers Falls, US
Amy L. Child · Saratoga Springs, US
George R. Mulfinger · Gansevoort, US

Key dates

Filing date	Dec 20, 2017
Grant date	Mar 19, 2019
Priority date	—
Expiry date	Dec 20, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH10D86/201
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A pFET includes a semiconductor-on-insulator (SOI) substrate; and a trench isolation within the SOI substrate, the trench isolation including a raised portion extending above an upper surface of the SOI substrate. A compressive channel silicon germanium (cSiGe) layer is over the SOI substrate. A strain retention member is positioned between at least a portion of the raised portion of the trench isolation and the compressive cSiGe layer. A gate and source/drain regions are positioned over the compressive cSiGe layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.