Biasing schemes for storage of bits in unreliable storage locations
US10241704B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2017 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Jul 31, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.